1. Field of Invention
This invention relates to digital logic test systems and more particularly to a system for rapidly and reliably identifying the existence of digital faults in a complex digital logic circuit system.
2. Description of the Prior Art
In the construction of printed circuit boards and other circuitry involving complex digital integrated circuits, faults occur due to poor connections, bad soldering and the like. Generally, complex digital logic circuitry is not accessible for testing purposes except at the terminals of the circuit board upon which the circuit system is mounted or at the terminals of the package in which the circuit system is encased. A great premium is placed on an ability to rapidly locate defects in logic circuitry and to reliably establish whether a particular system or unit under test is free of faults.
The diversity of types of individual circuit systems now available makes it generally impractical to provide dedicated devices for testing each particular type of circuit system. Therefore a number of general purpose methods and test devices have been developed for testing such circuit systems. For example, general purpose testers have been developed employing computer systems wherein a computer program is stored which simulates the operation of the digital logic under test for synchronous comparison therewith. These types of tests, although relatively reliable, are generally tedious to program and slow in operation.
Another type of test system developed is designed to compare directly the simultaneous response of a reference circuit system with the circuit system under test. This type of test system has major disadvantages. For example, a reference circuit system must be available, which is a major inconvenience in a field service environment, and the test system must be capable of connecting to two circuit systems simultaneously, which requires a second interface.
A third type of test system operates independently of the simultaneous response of a reference system. Such a tester operates according to what is generally known as the signature technique. According to this technique, a repeatable pseudo-random logic test pattern comprising the output of one or more bit pattern generators is provided to one or more of the input terminals of a circuit system to be tested. At the end of the test sequence, the response of the circuit system under test, a computed and coded signature word, is compared with the response of a reference, namely a reference signature word. The response may be displayed as a coded alpha-numeric pattern such as a combination of octal-numeric and alphabetic characters. The response of the system, the signature word, is documented for reference. The signature word of a known good circuit system is compared with the signature word of the circuit system under test. A discrepancy indicates the existence of faults in the circuit system under test.
Several types of signature systems are known to the art. One type is the transition count signature technique, in which logic level transitions of the output terminals or test point terminals of the circuit system under test is monitored for a fixed duration of test time. A representative device employing the transition counting technique hereinabove described is the Fluke Trendar Model 3020A Logictester manufactured by Fluke Trendar Corporation of Mountain View, California. The transition count technique, however, is limited in that faults due to timing problems and phase shift problems are not detected. For example, according to the transition count technique, the number of transitions at each terminal is counted. If one of the transitions is delayed relative to the transitions at another terminal, but the number of counts is unchanged, the fault goes undetected. Nevertheless, the transition count technique is valuable because it allows the test operator to determine the number of counts by which the circuit system under test differs from the reference signature, thereby obtaining an estimate of the severity of the error.
A further technique for testing digital circuit systems is the feedback signature method employed in a feedback shift register network. The most widely known feedback shift register technique is the cyclic redundancy check (CRC) technique developed for verifying the accuracy of digital communication. A description of representative cyclic redundancy check networks for testing digital circuits are found in U.S. Pat. No. 3,976,864, assigned to Hewlett-Packard Company of Palo Alto, California and U.S. Pat. No. 3,924,181, assigned to Hughes Aircraft Company, Culver City, California. A cyclic redundancy check network is capable of detecting timing and phase shift problems in a digital system. A mathematically pure implementation of the cyclic redundancy check technique has precisely definable fault detecting capabilities. Unfortunately, the resultant signature contains no indication of the degree of error detected or even of the length of the test pattern process. Consequently the operator is not given a "feel" for the severity of error encountered in the tested system, as can be obtained from the transition count technique.